
`timescale  1 ns/1 ps

module ${ip_name} #
(
    parameter               ${PARA1} = 128
)
(
    input   wire                csi_clk,
    input   wire                rsi_reset_n,

    input   wire [01:00]        avs_address,
    input   wire                avs_write,
    input   wire [31:00]        avs_writedata,
    output  reg  [${PARA1}-1:00]   coe_parameter_out
);

wire    [${PARA1}-1:00]             user_parameter;

// avalon-mm receive
${ip_name}_register ${ip_name}_registerEx01
(
    .csi_clk           (    csi_clk           ),
    .rsi_reset_n       (    rsi_reset_n       ),
    .avs_address       (    avs_address       ),
    .avs_write         (    avs_write         ),
    .avs_writedata     (    avs_writedata     ),

    .user_parameter    (    user_parameter    )
);

// user self-define logic
${ip_name}_logic ${ip_name}_logicEx01
(
    .csi_clk           (    csi_clk           ),
    .rsi_reset_n       (    rsi_reset_n       ),
    .parameter_in      (    user_parameter    ),
    .parameter_out     (    coe_parameter_out )
);


endmodule
